NucleusRV: A 32 bit RISC-V core

Note

This project is under active development.

NucleusRV is a 32-bit 5 stage pipelined RISC-V core written in Chisel. It implements I base ISA, M multiply and divide, and C compressed instructions (RV32IMC). NucleusRV has been taped out in Google’s sponsered OpenMPW-6 shuttle on SKY130nm process node.

The documentation is split into 3 sections.

The Overview section explores the features of NucleusRV from bird’s eye view.

The User Guide section provides information necessary to setup and run NucleusRV. It is aimed at software developers writing software for NucleusRV.

The Developer Guide section gives detailed explanation of source code and different design decisions. It highlights contribution guidelines and will be helpful for people making changes to NucleusRV