Get Started with NucleusRV

Learn how to clone NucleusRV, generate Verilog from Chisel sources, and run your first simulation with Verilator in under 10 minutes.

Clone the Repository

Clone the repository with submodules:

git clone --recurse-submodules https://github.com/merledu/nucleusrv.git
cd nucleusrv

Prepare Your Program

Generate a hex file from an assembly or C program using the provided tools:

cd tools
make PROGRAM=fibonacci
cd ..

Generate Verilog

Use the NRVDriver to generate Verilog from Chisel:

sbt "nucleusrv.components.NRVDriver \
  --imem tools/out/program.hex \
  --dmem tools/out/program.hex \
  --target-dir generated"

Compile with Verilator

Set NRV_ROOT and compile:

export NRV_ROOT=$PWD
cd generated
verilator --cc --exe --build --trace --no-timing $NRV_ROOT/tb_Top.cpp Top.v

Run the Simulation

./obj_dir/VTop

Inspect Waveforms

If tracing was enabled, waveforms are saved in the logs/ directory:

gtkwave logs/top.vcd