NucleusRV Documentation

NucleusRV is an open-source 32-bit 5-stage pipelined RISC-V core (RV32IMAFC) written in Chisel. It is designed for high configurability and ease of integration into FPGA and ASIC designs.

Table of Contents

• NucleusRV: RV32IMAFC Processor Core for FPGA & ASIC
  • Key Features
  • Supported ISA Extensions
  • Where to Go Next
  • What you can do with NucleusRV
• Get Started with NucleusRV
  • Clone the Repository
  • Prepare Your Program
  • Generate Verilog
  • Compile with Verilator
  • Run the Simulation
  • Inspect Waveforms
• Install NucleusRV Dependencies and Toolchain
  • Install Verilator
  • Install RISC-V GNU Toolchain
  • Install Java, sbt, and Scala
  • Verify Your Setup
• RISC-V ISA Extensions Supported by NucleusRV
  • Supported Extensions
  • Extension Details
  • MISA Register
• NucleusRV 5-Stage Pipeline Architecture
  • Pipeline Stages
  • Hazard Handling
  • Pipeline Registers
• NucleusRV Memory Interface: Instruction and Data Ports
  • Bundle Definitions
  • Handshake Protocol
  • Timing
• Configuring NucleusRV: Extensions and Core Options
  • The Configs Case Class
  • Parameter Reference
  • Instantiating with Custom Configuration
  • Common Configurations
• Simulate RISC-V Assembly Programs with NucleusRV
  • Write Your Assembly File
  • Assemble and Convert to Hex
  • Generate Verilog and Simulate
  • Verify Output
• Build and Run C Programs on NucleusRV
  • Create a Test Directory
  • Build with Make
  • Simulate
• Run RISC-V Architecture Compliance Tests
  • Setup the Environment
  • Run the Tests
  • Review Results
• Generate and View Waveforms with NucleusRV
  • Enabling Waveform Tracing
  • Where Waveforms are Saved
  • Opening Waveforms in GTKWave
  • Key Signals to Watch
• Integrate NucleusRV into an FPGA Design
  • Generate Synthesis-Ready Verilog
  • Connect the Core
  • Synthesis Tips
• CSR Address Map Reference for NucleusRV
  • Machine-Mode CSRs
  • Floating-Point CSRs
  • Performance Counters
  • Detailed Field Maps
• NucleusRV Configuration Options Reference
  • Case Class Definition
  • Parameter Details
• NucleusRV Pipeline Stages and Signal Reference
  • Stage 1: IF — Instruction Fetch
  • Stage 2: ID — Instruction Decode
  • Stage 3: EX — Execute
  • Stage 4: MEM — Memory Access
  • Stage 5: WB — Write Back
  • Top-level IO Port Reference